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30 v, low noise, rail-to-rail input/output, low power operational amplifiers data sheet ada4084-1 / ada4084-2 / ada4084-4 rev. h document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2011C2015 analog devices, inc. all rights reserved. technical support www.analog.com features rail-to-rail input/output low power: 0.625 ma typical per amplifier at 15 v gain bandwidth product: 15.9 mhz at a v = 100 typical unity-gain crossover: 9.9 mhz typical ?3 db closed-loop bandwidth: 13.9 mhz typical at 15 v low offset voltage: 100 v maximum (soic) unity-gain stable high slew rate: 4.6 v/s typical low noise: 3.9 nv/hz typical at 1 khz applications battery-powered instrumentation high-side and low-side sensing power supply control and protection telecommunications digital-to-analog converter (dac) output amplifiers analog-to-digital converter (adc) input buffers pin connection diagram 08237-001 notes 1. for the lfcsp package, the exposed pad must be connected to v?. 3 +in a 4 v? 1 out a 2 ?in a 6?in b 5+in b 8v+ 7out b ada4084-2 figure 1. ada4084-2 , 8-lead lfcsp (cp) see the pin configurations and function descriptions section for additional pin configurations and information about the pin functions. general description the ada4084-1 (single), ada4084-2 (dual), and ada4084-4 (quad) are single-supply, 10 mhz bandwidth amplifiers featuring rail-to-rail inputs and outputs. they are guaranteed to operate from +3 v to +30 v (or 1.5 v to 15 v). these amplifiers are well suited for single-supply applications requiring both ac and precision dc performance. the combination of wide bandwidth, low noise, and precision makes the ada4084-1 , ada4084-2 , and ada4084-4 useful in a wide variety of applications, including filters and instrumentation. other applications for these amplifiers include portable telecom- munications equipment, power supply control and protection, and use as amplifiers or buffers for transducers with wide output ranges. sensors requiring a rail-to-rail input amplifier include hall effect, piezoelectric, and resistive transducers. the ability to swing rail to rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios. the ada4084-1 , ada4084-2 , and ada4084-4 are specified over the industrial temperature range of ?40c to +125c. the single ada4084-1 is available in the 5-lead sot-23 and 8-lead soic; the dual ada4084-2 is available in the 8-lead soic, 8-lead msop, and 8-lead lfcsp surface-mount packages; and the ada4084-4 is offered in the 14-lead tssop and 16-lead lfcsp. the ada4084-1 , ada4084-2 , and ada4084-4 are members of a growing series of high voltage, low noise op amps offered by analog devices, inc. (see table 1). table 1. low noise op amps single dual quad voltage noise ad8597 ad8599 1.1 nv/hz ada4004-1 ada4004-2 ada4004-4 1.8 nv/hz ad8675 ad8676 2.8 nv/hz rail-to-rail output ad8671 ad8672 ad8674 2.8 nv/hz op27, op37 3.2 nv/hz ada4084-1 ada4084-2 ada4084-4 3.9 nv/hz rail-to-rail input/output
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 2 of 35 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin connection d iagram ................................................................ 1 general description ......................................................................... 1 revision history ........................................................................... 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 11 1.5 v characteristics ................................................................ 11 5 v characteristics ................................................................... 17 15 v characteristics ................................................................ 23 applic ations information .............................................................. 29 functional description .............................................................. 29 start - up characteristics ............................................................ 30 input protection ......................................................................... 30 output phase reversal ............................................................... 30 designing low noise circuits in single - supply applications .. 31 comparator operation .............................................................. 31 outline dimensions ....................................................................... 32 ordering g uide .......................................................................... 35
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 3 of 35 revision history 8 /15 rev. g to rev. h added 5 - lead sot - 23 ....................................................... universa l changes to pin connection diagram section , figure 1, and general description section ............................................................ 1 deleted figure 3; renumbered sequentially ................................. 1 changes to large signal voltage gain parameter, table 2 .......... 4 changes to large signal voltage gain parameter, table 3 .......... 5 changes to large signal voltage gain parameter, table 4 .......... 6 changes to table 6 ............................................................................ 7 moved figure 3 .................................................................................. 8 added pin configurations and function descriptions section, figure 4, figure 5, table 7, tabl e 8 , and table 9 ; renumbered sequentially ........................................................................................ 8 added figure 6 , figure 7 , figure 8 , table 10, and table 11 ......... 9 moved figure 9 ................................................................................ 1 0 added table 1 2 ................................................................................ 10 added figure 1 1 and figure 1 5 ..................................................... 1 1 added figure 4 2 and figure 4 6 ..................................................... 1 7 added figure 7 3 and figure 7 7 ..................................................... 2 3 updated outline dimensions ........................................................ 32 changes to ordering guide ........................................................... 35 6/15 rev. f to rev. g changes to figure 96 and figure 97 ............................................. 24 1/15 rev. e to rev. f moved revision history ................................................................... 3 changes to table 5 ............................................................................ 7 changes to ordering guide ........................................................... 29 7 /14 rev. d to rev. e added ada4 0 8 4 - 1 ............................................................ universal added figure 1; renumbered sequentially ................................... 1 changes to output voltage high parameter, table 2 ................... 3 changes to current noise density parameter, table 3 ................ 4 changes to current noise density parameter, table 4 ................ 5 changes to figure 8 caption, and figure 9 to figure 11 ............. 7 changes to figure 13 ........................................................................ 8 changes to figure 21 ........................................................................ 9 added figure 31; renumbered sequentially ............................... 1 1 changes to figure 30 caption, and figure 32 to figure 3 4 ....... 1 1 changes to figure 36 caption to figure 39 caption .................. 12 changes to figure 50 ...................................................................... 1 4 added figure 60 .............................................................................. 1 6 changes to figure 59 caption, figure 62 , and figure 63 ........... 1 6 changes to figure 65 caption to figure 68 caption .................. 17 changes to figure 79 ...................................................................... 19 added figure 89 .............................................................................. 2 1 changes to figure 88 caption, figure 91 c aption , and figure 92 c aption ............................................................................ 2 1 changes to ordering guide ........................................................... 28 11 /13 rev. c to rev. d added 14 - lead tssop and 16 - lead lfcsp package s ....... universal added ada40 8 4 - 4 ..................................................................... universal change to features section and applications section ................. 1 added figure 2 and figure 3 ; renumbered sequentially ............ 1 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 4 changes to table 4 ............................................................................ 5 changes to table 5 and table 6 ....................................................... 6 changes to typical performance characteristics section ........... 7 updated outline dime nsions ........................................................ 27 changes to ordering guide ........................................................... 28 4 /13 rev. b to rev. c changes to figure 48 caption ....................................................... 15 updated outline dimensions ........................................................ 25 6 /12 rev. a to rev. b added lfc s p package ...................................................... universal changes to figure 1 .......................................................................... 1 changes to output voltage high parameter, table 4 ................... 5 added figure 5 and figure 7, renumbered sequentially ............ 7 added figure 30 and figure 32 ..................................................... 12 added figure 55 and figure 57 ..................................................... 17 added startup characteristics section ........................................ 23 moved figure 78 .............................................................................. 23 changes to output phase reversal section and comparator operation section ........................................................................... 24 updated outline dimensions ........................................................ 25 changes to ordering guide ........................................................... 2 6 2/ 12 rev. 0 to rev. a changes to data sheet title ............................................................. 1 changes to voltage range in general description ...................... 1 changes to supply current/amplifier parameter, table 2 .......... 3 changes to common - mode rejection rati o parameter, table 3 .. 4 changes to common - mode rejection ratio parameter, table 4 .. 5 changes to figure 2 .......................................................................... 6 changes to figure 24 ...................................................................... 10 changes to figure 32 ...................................................................... 12 changes to figure 47 ...................................................................... 14 changes to figure 55 ...................................................................... 16 changes to figure 62 ...................................................................... 17 changes to figure 73 ...................................................................... 20 10/ 11 revision 0: initial version
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 4 of 35 specifications electrical character istics v s y = 3 v, v cm = 1.5 v, t a = 25c, unless otherwise noted. table 2. parameter symbol test conditions /comments min typ max unit input characteristics offset voltage v os soic package 20 100 v ? 40c t a +125c 200 v sot - 23, msop , tsso p package s 50 130 v ? 40c t a +125c 250 v ada4084 - 2 lfcsp package 80 200 v ? 40c t a +125c 300 v offset voltage drift t /t ? 40c t a +125c 0.5 1.75 v/c offset voltage matching t a = 25c 150 v ada4084 - 4 lfcsp package 200 v input bias current i b 140 250 na ? 40c t a +125 c 400 na input offset current i os 5 25 na ? 40c t a +125c 50 na input voltage range 0 3 v common - mode rejection ratio cmrr v cm = 0 v to 3 v 64 88 db ? 40c t a +125c 60 db large signal voltage gain a vo r l = 2 k? , 0.5 v v o ut 2.5 v 100 104 db ? 40c t a +125c 97 db input impedance differential 100||1.1 k?||pf common mode 80||2.9 m?||pf output characteristics output voltage high v oh r l = 10 k? to v cm 2.9 0 2.95 v ? 40c t a +125c 2.8 0 v r l = 2 k? to v cm 2.8 5 2.9 v ? 40c t a +125c 2.7 0 v output voltage low v ol r l = 10 k? to v cm 10 20 mv ? 40c t a +125c 40 mv r l = 2 k? to v cm 20 30 mv ? 40c t a +125c 50 mv short - circuit current i sc ? 17/+10 ma closed - loop output impedance z out f = 1 khz, a v = 1 0.1 ? power supply power supply rejection ratio psrr v sy = 1.25 v to 1.75 v 100 110 db ? 40c t a +125c 90 db supply current per amplifier i sy i o ut = 0 ma 0. 565 0. 650 m a ? 40c t a +125c 0. 950 m a dynamic performance slew rate sr r l = 2 k? 2.0 2.6 v/s gain bandwidth product gbp v in = 5 mv p - p, r l = 10 k?, a v = 100 15.4 mhz unity - gain crossover ugc v in = 5 mv p - p, r l = 10 k?, a v = 1 8.08 mhz phase margin m 86 degrees ?3 db closed - loop bandwidth ?3 db a v = 1, v in = 5 mv p - p 12.3 mhz settling time t s a v = 1 0 , v in = 2 v p - p , 0.1% 4 s total harmonic distortion plus noise thd + n v in = 300 m v rms , r l = 2 k?, f = 1 khz 0.009 % noise performance voltage noise e n p - p 0.1 hz to 10 hz 0.14 v p - p voltage noise density e n f = 1 khz 3.9 nv/hz current noise density i n f = 1 khz 0.55 pa/hz
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 5 of 35 v s y = 5 .0 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 3. parameter symbol test conditions /comments min typ max unit input characteristics offset voltage v os soic package 30 100 v ? 40c t a +125c 200 v sot - 23, msop, tssop packages 60 130 v ? 40c t a +125c 250 v ada4084 - 2 lfcsp package 90 200 v ? 40c t a +125c 300 v offset voltage drift v os /t ? 40c t a +125c 0.5 1.75 v /c offset voltage matching t a = 25c 150 v ada4084 - 4 lfcsp package 200 v input bias current i b 140 250 na ? 40c t a +125c 400 na input offset current i os 5 25 na ? 40c t a +125c 50 na input voltage range ?5 +5 v common - mode rejection ratio cmrr v cm = 4 v , ?40c t a +125c 106 124 db v cm = 5 v 76 db v cm = 5 v , ? 40c t a +125c 70 db large signal voltage gain a vo r l = 2 k?, ?4 v v o ut 4 v 108 112 db ? 40c t a +125c 103 db input impedance differential 100||1.1 k?||pf common mode 200||2.5 m?||pf output characteristics output voltage high v oh r l = 10 k? to v cm 4.9 4.95 v ? 40c t a +125c 4.8 v r l = 2 k? to v cm 4.8 4.85 v ? 40c t a +125c 4.7 v output voltage low v ol r l = 10 k? to v cm ?4.95 ? 4.9 v ? 40c t a +125c ? 4.8 v r l = 2 k? to v cm ?4.95 ? 4.8 v ? 40c t a +125c ? 4.7 v short - circuit current i sc ?24/+17 ma closed - loop output impedance z out f = 1 khz, a v = 1 0.1 ? power supply power supply rejection ratio psrr v sy = 2 v to 18 v 110 120 db ? 40c t a +125c 105 db supply current per amplifier i sy i o ut = 0 ma 0.595 0.700 ma ? 40c t a +125c 1.00 ma dynamic performance slew rate sr r l = 2 k? to v cm 2.4 3.7 v/s gain bandwidth product gbp v in = 5 mv p - p, r l = 10 k?, a v = 100 15.9 mhz unity - gain crossover ugc v in = 5 mv p - p, r l = 10 k?, a v = 1 9.6 mhz phase margin m 85 degrees ?3 db closed - loop bandwidth ?3 db a v = 1, v in = 5 mv p - p 13.9 mhz settling time t s a v = 10, v in = 8 v p - p, 0.1% 4 s total harmonic distortion plus noise thd + n v in = 2 v rms, r l = 2 k?, f = 1 khz 0.003 % noise performance voltage noise e n p - p 0.1 hz to 10 hz 0.14 v p - p voltage noise density e n f = 1 khz 3.9 nv/hz current noise density i n f = 1 khz 0.55 pa/hz
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 6 of 35 v s y = 15.0 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 4. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os soic package 40 100 v ? 40c t a +125c 200 v sot - 23, msop, tssop packages 70 130 v ? 40c t a +125c 250 v ada4084 - 2 lfcsp package 100 200 v ? 40c t a +125c 300 v offset voltage drift v os /t 0.5 1.75 v /c offset voltage matching t a = 25c 150 v ada4084 - 4 lfcsp package 200 v input bias current i b 140 250 na ? 40c t a +125c 400 na input offset current i os 5 25 na ? 40c t a +125c 50 na input voltage range ?15 +15 v common - mode rejection ratio cmrr v cm = 14 v , ?40c t a +125c 106 124 db v cm = 15 v 85 db v cm = 15 v, ? 40c t a +125c 80 db large signal voltage gain a vo r l = 2 k?, ?13.5 v v o ut +13.5 v 110 117 db ? 40c t a +125c 105 db input impedance differential 100||1.1 k?||pf common mode 200||2.5 m?||pf output characteristics output voltage high v oh r l = 10 k? to v cm 14.8 5 14.9 v ? 40c t a +125c 14.8 v r l = 2 k? to v cm 14.5 14.6 v ? 40c t a +125c 14. 0 v output voltage low v ol r l = 10 k? to v cm ?14.95 ? 14.9 v ? 40c t a +125c ? 14.8 v r l = 2 k? to v cm ?14.9 ? 14. 8 v ? 40c t a +125c ? 14.7 v short - circuit current i sc 30 ma closed - loop output impedance z out f = 1 khz, a v = +1 0.1 ? power supply power supply rejection ratio psrr v s y = 2 v to 18 v 110 120 db ? 40c t a +125c 105 db supply current per amplifier i sy i o ut = 0 ma 0. 625 0. 750 m a ? 40c t a +125c 1 . 050 m a dynamic performance slew rate sr r l = 2 k? 2.4 4.6 v/s gain bandwidth product gbp v in = 5 mv p - p, r l = 10 k?, a v = 100 15.9 mhz unity - gain crossover ugc v in = 5 mv p - p, r l = 10 k?, a v = 1 9.9 mhz phase margin m 86 degrees ?3 db closed - loop bandwidth ?3 db a v = 1, v in = 5 mv p - p 13.9 mhz settling time t s a v = 1 0 , v in = 10 v p - p , 0.1% 4 s total harmonic distortion plus noise thd + n v in = 5 v rms , r l = 2 k?, f = 1 khz 0.003 % noise performance voltage noise e n p - p 0.1 hz to 10 hz 0.1 v p - p voltage noise density e n f = 1 khz 3.9 nv/hz current noise density i n f = 1 khz 0.55 pa/hz
data sheet ada4084-1/ada4084-2/ada4084-4 rev. h | page 7 of 35 absolute maximum ratings table 5. parameter rating supply voltage 18 v input voltage v? v in v+ differential input voltage 1 0.6 v output short-circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c esd human body model 2 4.5 kv machine model 3 200 v field-induced charged-device model (ficdm) 4 1.25 kv 1 for input differential vo ltages greater than 0.6 v, limit the input current to less than 5 ma to prevent degradation or destruction of the input devices. 2 applicable standard: mil-std-883, method 3015.7. 3 applicable standard: jesd22-a115-a (esd machine model standard of jedec). 4 applicable standard: jesd22-c101-c (esd ficdm standard of jedec). stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the device soldered on a 4-layer jedec standard printed circuit board (pcb) with zero airflow. table 6. thermal resistance package type ja jc unit 5-lead sot-23 (rj-5) 219.4 155.6 c/w 8-lead soic_n (r-8) 121 43 c/w 8-lead msop (rm-8) 142 45 c/w 8-lead lfcsp (cp-8-12) 1, 3 84 40 c/w 14-lead tssop (ru-14) 112 43 c/w 16-lead lfcsp (cp-16-26) 2, 3 55 30 c/w 1 values are based on 4-layer (2s2p) jedec standard pcb, with four thermal vias. exposed pad soldered to pcb. 2 values are based on 4-layer (2s2p) jedec standard pcb, with nine thermal vias. exposed pad soldered to pcb. 3 jc measured on top of package. esd caution d2 d101 d100 d5 d4 d1 q1 q4 q3 q24 q21 d20 q13 q18 q19 q23 q2 folded cascade v ee v out v cc v bias mirror 08237-002 r4 r5 r6 r7 c2 c1 r1 r2 r3 figure 2. simplified schematic
ada4084 - 1/ada4084 - 2/ada4084 -4 data sheet rev. h | page 8 of 35 pin configuration s and function descrip tions nic 1 ?in 2 +in 3 v? 4 nic 8 v+ 7 out 6 nic 5 notes 1. nic = not internally connected. ada4084-1 top view (not to scale) 08237-101 f igure 3 . ada4084 -1 , 8 - lead soic (r) table 7. 8- lead soic, ada4084 -1 pin function descriptions pin no. mnemonic description 1 nic not internally connected 2 ?in negative input 3 +in positive input 4 v? negative supply 5 nic not internally connected 6 out output 7 v+ positive supply 8 nic not internally connected out 1 v? 2 +in 3 v+ 5 ada4084-1 ?in 4 08237-301 f igure 4 . ada4084 -1 , 5- lead so t- 23 (r j) table 8. 5 - lead sot - 23, ada4084 -1 pin function descriptions pin no. mnemonic description 1 out output 2 v? negative supply 3 +in positive input 4 ?in negative input 5 v+ positive supply 08237-104 notes 1. for the lfcsp package, the exposed pad must be connected to v?. +in a v? out a ?in a ?in b +in b v+ out b 3 4 1 2 6 5 8 7 ada4084-2 top view (not to scale) f igure 5 . ada4084 -2 , 8 - lead lfcsp (cp) table 9. 8-lead lfcsp, ada4 084-2 pin function descriptions pin no. mnemonic description 1 out a output, channel a 2 ?in a negative input, channel a 3 +in a positive input, channel a 4 v? negative supply 5 +in b positive input, channel b 6 ?in b negative in put, channel b 7 out b out put, channel b 8 v+ positive supply epad exposed pad. for the lfcsp package, t he exposed pad must be connected to v?.
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 9 of 35 08237-302 +in a v? out a ?in a ?in b +in b v+ out b 1 2 3 4 8 7 6 5 ada4084-2 t op view (not to scale) figure 6 . ada4084 - 2 , 8 - lead msop (rm) 08237-303 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4084-2 top view (not to scale) figure 7 . ada4084 - 2 , 8 - lead soic (r) table 10. 8 - lead msop, 8- lead soic, ada4084 - 2 pin function descriptions pi n no. mnemonic description 1 out a output, channel a 2 ?in a negative input, channel a 3 +in a positive input, channel a 4 v? negative supply 5 + in b positive input, channel b 6 ?in b negative input , channel b 7 out b output , channel b 8 v+ positive supply b out b +in b ?in b v+ ?in a +in a out a out c +in c ?in c v? ?in d +in d out d 1 2 3 4 5 6 7 14 13 12 1 1 10 9 8 ada4084-4 t o p view (not to scale) 08237-102 figure 8 . ada4084 - 4 , 14 - lead tssop (ru ) table 11. 14 - lead tssop , ada4804 -4 pin function descriptions pin no. mnemonic description 1 out a output, channel a 2 ?in a negative input, channel a 3 +in a positive input, channel a 4 v+ positive supply 5 +in b positive input, channel b 6 ?in b negative input, channel b 7 out b output, channel b 8 out c output, channel c 9 ?in c negative input, channel c 10 +in c positive input, channel c 11 v? negative supply 12 +in d positive input, channel d 13 ?in d negative input, channel d 14 out d output, channel d
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 10 of 35 12 11 10 1 3 4 ?in d +in d v? 9 +in c ?in a v+ 2 +in a +in b 6 out b 5 ?in b 7 out c 8 ?in c 16 nic 15 out a 14 out d 13 nic top view ada4084-4 notes 1. nic = not internally connected. 2. for the lfcsp package, the exposed pad must be connected to v?. 08237-103 figure 9 . ada4084 - 4 , 16 - lead lfcsp (cp) table 12. 16 - lead lfcsp, ada4084-4 pin funct ion descriptions pin no. mnemonic description 1 ?in a negative input channel a 2 +i n a positive input, channel a 3 v+ positive supply 4 +in b positive input, channel b 5 ?in b negative input, channel b 6 out b output, channel b 7 out c output, channel c 8 ?in c negative input, channel c 9 +in c positive input, channel c 10 v? negative supply 11 +in d positive input, channel d 1 2 ?in d negative input, channel d 13 nic not internally connected 14 out d output, channel d 15 out a output, channel a 16 nic not internally connected
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 11 of 35 typical performance characteristics t a = 25c, unless otherwise noted. 1.5 v characteristi cs 120 0 ?100 ?50 50 0 100 number of amplifiers v os (v) 20 40 60 80 100 v sy = 1.5v t a = 25c r l = ?25 25 ?75 75 08237-003 figure 10 . input offset voltage (v os ) distribution, soic 0 10 20 30 40 50 60 70 80 90 100 ?100 ?75 ?50 ?25 0 25 50 75 100 number of amplifiers v os (v) v sy = 1.5v t a = 25c r l = 08237-306 figure 11 . input offset voltage (v os ) distribution, sot - 23 50 0 ?100 ?50 ?25 25 ?75 75 50 0 100 number of amplifiers v os (v) v sy = 1.5v t a = 25c r l = 5 10 15 20 25 30 35 40 45 08237-004 figure 12 . input offset voltage (v os ) distribution, msop and tssop 0 50 100 150 200 ?200 ?150 ?100 ?50 0 50 100 number of amplifiers v os (v) 08237-081 v sy = 1.5v t a = 25c r l = 60 0 0 2.0 number of amplifiers tcv os (v/c) v sy = 1.5v r l = C40c t a +125c 10 20 30 40 50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 08237-005 figure 14 . tcv os distribution, soic, msop, and tssop 0 2 4 6 8 10 12 14 16 18 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers tcv os (v / c) v sy = 1.5v r l = ?40c t a +125c 08237-309 figure 15 . tcv os distribution, sot - 23
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 12 of 35 0 5 10 15 20 25 30 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers tcv os ( v/c) 08237-082 v sy = 1.5v r l = C40c t a +125c figure 16 . tcv os distribution, lfcsp 500 ?500 ?1.50 ?1.00 ?0.50 0 1.50 1.00 0.50 input offset voltage (v) common-mode voltage (v) ?400 ?300 ?200 ?100 0 100 200 300 400 v sy = 1.5v t a = 25c r l = 08237-006 figure 17 . input offset voltage vs. common - mode voltage ?10 0 ?7 5 ?5 0 ?2 5 0 2 5 5 0 7 5 10 0 ?5 0 ?2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 i n p u t off se t vo l t a g e ( v) t emper a t ur e ( c ) 08237 - 10 8 v sy = 1.5v figure 18 . input offset voltage vs. temperature ?250 ?200 ?150 ?100 50 ?50 ?25 0 25 50 75 100 125 150 08237-213 v sy = 1.5v v cm = 0v r l = input bias current (na) temperature (c) i b + i b ? figure 19 . input bias current vs. temperature 600 ?600 ?1.5 ?1.0 1.0 ?0.5 0.5 0 1.5 input bias current (na) v cm (v) ?400 ?200 0 200 400 t a = +85c t a = +25c t a = +125c t a = ?40c v sy = 1.5v 08237-008 figure 20 . input bias current vs. v cm for various temperatures 1000 100 10 1 0.001 0.01 0.1 1 10 v do (mv) source current (ma) v sy = 1.5v t a = 25c (v+) ? v oh 08237-009 figure 21 . dropout voltage (v do ) vs. source current
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 13 of 35 1000 100 10 1 0.001 0.01 0.1 1 10 v do (mv) sink current (ma) v sy = 1.5v t a = 25c v ol ? (v?) 08237-010 figure 22 . dropout voltage (v do ) vs. sink current 120 ?40 270 ?90 0.1 100k gain (db) phase (degrees) frequency (khz) ?45 0 45 90 135 180 225 ?20 20 0 40 60 80 100 1 10 100 1k 10k v sy = 1.5v t a = 25c r l = 10k? 08237-0 1 1 figure 23 . open - loop gain and phase vs. frequency 60 ?20 10 100m gain (db) frequency (hz) ?10 0 10 20 30 40 50 100 1k 10k 100k 10m 1m a v = +100 a v = +10 a v = +1 v sy = 1.5v t a = 25c 08237-012 figure 24 . closed - loop gain vs. frequency 1000 100 10 1 0.10 0.01 10 100m z out (?) frequency (hz) 100 1k 10k 100k 10m 1m v sy = 1.5v t a = 25c a v = +10 a v = +100 a v = +1 08237-013 figure 25 . output impedance (z out ) vs. frequency 140 ?20 10 100m psrr (db) frequency (hz) 0 20 40 60 80 100 120 100 1k 10k 100k 10m 1m v sy = 1.5v t a = 25c psrr? psrr+ 08237-014 figure 26 . psrr vs. frequency 140 120 100 80 60 40 20 0 10 100m cmrr (db) frequency (hz) 100 1k 10k 100k 10m 1m v sy = 1.5v t a = 25c 08237-221 figure 27 . cmrr vs. frequency
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 14 of 35 1.5 1.0 0.5 0 ?1.5 ?1.0 ?0.5 0 2 4 6 8 10 12 14 16 18 voltage (v) time (s) v sy = 1.5v t a = 25c r l = 2k? c l = 100pf 08237-016 figure 28 . large signal transient response 80 60 40 20 0 ?80 ?60 ?40 ?20 0 18 voltage (mv) time (s) v sy = 1.5v t a = 25c r l = 2k? c l = 100pf 08237-017 2 4 6 8 10 12 14 16 figure 29 . small signal transient response 2 ?10 ?8 ?6 ?4 ?2 0 0.08 ?0.04 ?0.02 0 0.02 0.04 0.06 ?1 0 2 1 4 3 7 8 6 5 9 voltage (v) voltage (v) time (s) v sy = 1.5v t a = 25c output input 08237-018 figure 30 . settling time 10 4 1 1 10 100 1k 10k 100k voltage noise density (nv/hz) frequency (hz) v sy = 1.5v t a = 25c 08237-019 figure 31 . voltage noise density vs. frequency 60 50 40 30 20 10 0 1 1000 100 10 overshoot (%) load capacitance (pf) v sy = 1.5v v in = 100mv p-p r l = 2k? t a = 25c os+ os? 08237-020 figure 32 . overshoot vs. load capacitance 80 ?80 0 1 2 3 4 5 6 7 8 9 10 voltage noise (nv) time (seconds) ?60 ?40 ?20 0 20 40 60 v sy = 1.5v t a = 25c 08237-021 figure 33 . voltage noise, 0.1 hz to 10 hz
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 15 of 35 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 100 1k 10k 100k channel separation (db) frequency (hz) v sy = 1.5v t a = 25c v in = 1v p-p 08237-022 2k ? + 10v p-p ch a v cc v ee ? + 2k 10k 1k ch b, ch c, ch d v cc v ee figure 34 . channel separation vs. frequency 1 0.1 0.01 thd + n (%) 0.001 0.0001 0.001 0.01 amplitude (v rms ) 0.1 1 v sy = 1.5v t a = 25c r l = 10k v in at 1khz 08237-125 figure 35 . thd + n vs. amplitude 0.01 thd + n (%) 0.001 0.01 0.1 frequenc y (khz) 1 10 100 v sy = 1.5v t a = 25c v in = 300mv rms 500khz filter r l = 10k r l = 2k 08237-126 figure 36 . thd + n vs. frequency, 500 khz filter 0.1 0.01 0.001 0.0001 10 100 1k 10k 100k thd + n (%) frequency (hz) 08237-231 v sy = 1.5v t a = 25c v in = 300mv rms 80khz filter r l = 2k r l = 10k 2.0 ?2.0 0 1000 voltage (v) time (s) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 100 200 300 400 500 600 700 800 900 v sy = 1.5v t a = 25c output input 08237-025 figure 38 . no phase reversal 0.5 ?2.0 ?1.5 ?1.0 ?0.5 0 4 ?1 0 1 2 3 ?2 0 4 2 8 6 14 16 12 10 18 voltage (v) voltage (v) time (s) v sy = 1.5v t a = 25c output 08237-233 input figure 39 . positive 50% overload recovery
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 16 of 35 0.5 ?2.0 ?1.5 ?1.0 ?0.5 0 3 ?2 ?1 0 1 2 ?2 0 4 2 8 6 14 16 12 10 18 voltage (v) voltage (v) time (s) v sy = 1.5v t a = 25c output 08237-234 input figure 40 . negative 50% overload recovery
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 17 of 35 5 v characteristics 120 0 ?100 ?50 50 ?25 25 0 ?75 75 100 number of amplifiers v os (v) 20 40 60 80 100 v sy = 5v t a = 25c r l = 08237-026 figure 41 . input offset voltage (v os ) distribution, soic 0 20 40 60 80 100 120 ?100 ?75 ?50 ?25 0 25 50 75 100 number of amplifiers v os (v) v sy = 5v t a = 25c r l = 08237-335 figure 42 . input offset voltage (v os ) distribution, sot - 23 60 0 ?100 100 number of amplifiers v os (v) 10 20 30 40 50 ?50 50 ?25 25 0 ?75 75 v sy = 5v t a = 25c r l = 08237-027 figure 43 . input offset voltage (v os ) distribution, msop and tssop 0 50 100 150 200 250 ?200 ?150 ?100 ?50 0 50 100 number of amplifiers v os (v) 08237-080 v sy = 5v t a = 25c r l = 50 0 0 2.0 number of amplifiers tcv os (v/c) 5 10 15 20 25 30 35 40 45 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v sy = 5v r l = C40c t a +125c 08237-028 figure 45 . tcv os distribution, soic, msop, and tssop 0 2 4 6 8 10 12 14 16 18 20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 number of amplifiers tcv os (v / c) v sy = 5v r l = ?40c t a +125c 08237-338 figure 46 . tcv os distribution for sot - 23
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 18 of 35 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers tcv os ( v/c) 0 5 10 15 20 25 30 35 08237-084 v sy = 5v r l = C40c t a +125c figure 47 . tcv os distribution, lfcsp 600 ?600 ?5 5 input offset voltage (v) common-mode voltage (v) ?400 ?500 ?300 ?200 ?100 0 100 200 300 400 500 v sy = 5v t a = 25c r l = ?4 ?3 ?2 ?1 0 1 2 3 4 08237-029 figure 48 . input offset voltage vs. common - mode voltage ?10 0 ?7 5 ?5 0 ?2 5 0 2 5 5 0 7 5 10 0 ?5 0 ?2 5 0 2 5 5 0 7 5 10 0 12 5 15 0 i n p u t off se t vo l t a g e ( v) t emper a t ur e ( c ) 08237 - 13 3 v sy = 5v figure 49 . input offset voltage vs. temperature ?50 ?100 ?150 ?200 ?250 ?40 125 input bias current (na) temperature (c) ?25 ?10 5 20 35 50 65 80 95 110 v sy = 5v v cm = 0v r l = i b + i b ? 08237-030 figure 50 . input bias current vs. temperature 800 ?800 ?5 5 input bias current (na) v cm (v) ?400 ?600 ?200 0 200 400 600 t a = +125c t a = ?40c v sy = 5v ?4 ?3 ?2 ?1 0 1 2 3 4 t a = +25c t a = +85c 08237-031 figure 51 . input bias current vs. v cm for various temperatures 1000 100 10 1 0.001 0.01 0.1 1 10 v do (mv) source current (ma) v sy = 5v t a = 25c (v+) ? v oh 08237-032 figure 52 . dropout voltage (v do ) vs. source current
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 19 of 35 1000 100 10 1 0.001 0.01 0.1 1 10 v do (mv) sink current (ma) v sy = 5v t a = 25c v ol ? (v?) 08237-033 figure 53 . dropout voltage (v do ) vs. sink current 120 ?40 270 ?90 0.1 100k gain (db) phase (degrees) frequency (khz) ?45 0 45 90 135 180 225 ?20 20 0 40 60 80 100 1 10 100 1k 10k v sy = 5v t a = 25c r l = 10k? 08237-034 figure 54 . open - loop gain and phase vs. frequency 60 ?20 10 100m gain (db) frequency (hz) ?10 0 10 20 30 40 50 100 1k 10k 100k 10m 1m v sy = 5v t a = 25c 08237-035 a v = +100 a v = +10 a v = +1 figure 55 . closed - loop gain vs. frequency 1000 100 10 1 0.10 0.01 10 100m z out (?) frequency (hz) 100 1k 10k 100k 10m 1m v sy = 5v t a = 25c a v = +100 a v = +1 a v = +10 08237-036 figure 56 . output impedance (z out ) vs. frequency 140 ?20 10 100m psrr (db) frequency (hz) 0 20 40 60 80 100 120 100 1k 10k 100k 10m 1m v sy = 5v t a = 25c psrr? psrr+ 08237-037 figure 57 . psrr vs. frequency 140 120 100 80 60 40 20 0 10 100m cmrr (db) frequency (hz) 100 1k 10k 100k 10m 1m v sy = 5v t a = 25c 08237-221 figure 58 . cmrr vs. frequency
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 20 of 35 5 ?5 voltage (v) time (s) v sy = 5v t a = 25c r l = 2k? c l = 100pf ?4 ?3 ?2 ?1 0 1 2 3 4 08237-039 0 18 2 4 6 8 10 12 14 16 figure 59 . large signal transient response 80 60 40 20 0 ?80 ?60 ?40 ?20 voltage (mv) time (s) v sy = 5v t a = 25c r l = 2k? c l = 100pf 08237-040 0 10 2 3 1 4 6 7 5 8 9 figure 60 . small signal transient response 10 ?25 ?20 ?5 ?10 ?15 0 5 0.16 ?0.12 ?0.08 ?0.04 0 0.04 0.08 0.12 ?2 0 2 4 8 6 18 16 12 10 14 voltage (v) voltage (v) time (s) v sy = 5v t a = 25c output input 08237-041 figure 61 . settling time 10 1 1 10 100 1k 10k 100k voltage noise density (nv/hz) frequency (hz) v sy = 5v t a = 25c 08237-042 4 figure 62 . voltage noise density vs. frequency 60 50 40 30 20 10 0 1 1000 100 10 overshoot (%) load capacitance (pf) v sy = 5v v in = 100mv p-p r l = 2k? t a = 25c os+ os? 08237-043 figure 63 . overshoot vs. load capacitance 80 ?80 0 1 2 3 4 5 6 7 8 9 10 voltage noise (nv) time (seconds) ?60 ?40 ?20 0 20 40 60 v sy = 5v t a = 25c 08237-044 figure 64 . voltage noise, 0.1 hz to 10 hz
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 21 of 35 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 100 1k 10k 100k channel separation (db) frequency (hz) v sy = 5v t a = 25c v in = 5v p-p 08237-045 2k ? + 10v p-p ch a v cc v ee ? + 2k 10k 1k ch b, ch c, ch d v cc v ee figure 65 . channel separation vs. frequency 1 0.1 0.01 thd + n (%) 0.001 0.0001 0.001 0.01 amplitude (v rms ) 0.1 1 v sy = 5v t a = 25c r l = 10k v in at 1khz 08237-150 figure 66 . thd + n vs. amplitude 1 thd + n (%) 0.001 0.01 0.1 0.0001 0.01 0.1 frequenc y (khz) 1 10 100 v sy = 5v t a = 25c v in = 2v rms 500khz filter r l = 10k r l = 2k 08237-151 figure 67 . thd + n vs. frequency, 500 khz filter 0.1 0.01 0.001 0.00001 0.0001 10 100 1k 10k 100k thd + n (%) frequency (hz) 08237-260 v sy = 5v t a = 25c v in = 300mv rms 80khz filter r l = 2k r l = 10k 6 4 2 ?4 ?2 ?6 0 1000 voltage (v) time (s) 0 100 200 300 400 500 600 700 800 900 v sy = 5v t a = 25c output input 08237-048 figure 69 . no phase reversal 1 ?5 ?4 ?3 ?2 ?1 0 10 ?2 0 2 4 6 8 ?2 0 4 2 8 6 14 16 12 10 18 voltage (v) voltage (v) time (s) v sy = 5v t a = 25c 08237-262 input output figure 70 . positive 50% overload recovery
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 22 of 35 1 ?5 ?4 ?3 ?2 ?1 0 6 ?6 ?4 ?2 0 2 4 ?2 0 4 2 8 6 14 16 12 10 18 voltage (v) voltage (v) time (s) v sy = 5v t a = 25c 08237-263 input output figure 71 . negative 50% overload recovery
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 23 of 35 15 v characteristic s 100 0 ?100 ?50 50 ?25 25 0 ?75 75 100 number of amplifiers v os (v) 20 30 10 40 50 60 70 80 90 v sy = 15v t a = 25c r l = 08237-049 figure 72 . input offset voltage (v os ) distribution, soic 0 10 20 30 40 50 60 70 80 90 100 ?100 ?75 ?50 ?25 0 25 50 75 100 number of amplifiers v os (v) v sy = 1.5v t a = 25c r l = 08237-364 figure 73 . input offset voltage (v os ) distribution, sot - 23 60 0 ?100 100 number of amplifiers v os (v) 10 20 30 40 50 ?50 50 ?25 25 0 ?75 75 v sy = 15v t a = 25c r l = 08237-050 figure 74 . input offset voltage (v os ) distribution, msop and tssop 0 50 100 150 200 ?200 ?150 ?100 ?50 0 50 100 number of amplifiers v os (v) 08237-079 v sy = 15v t a = 25c r l = 60 0 0 2.0 number of amplifiers tcv os (v/c) 10 20 30 40 50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v sy = 15v r l = C40c t a +125c 08237-051 figure 76 . tcv os distribution, soic, msop, and tssop 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers v sy = 15v r l = ?40c t a +125c tcv os (v) 08237-367 figure 77 . tcv os distribution, sot - 23
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 24 of 35 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 number of amplifiers tcv os ( v/c) 0 5 10 15 20 25 30 08237-085 v sy = 15v r l = C40c t a +125c figure 78 . tcv os distribution, lfcsp 600 ?600 ?15 ?10 ?5 5 15 10 input offset voltage (v) common-mode voltage (v) ?400 ?500 ?300 ?200 ?100 0 100 200 300 400 500 v sy = 15v t a = 25c r l = 0 08237-052 figure 79 . input offset voltage vs. common - mode voltage ?100 ?75 ?50 ?25 0 25 50 75 100 ?50 ?25 0 25 50 75 100 125 150 input offset vo lt age ( v) temper a ture (c) 08237-165 v sy = 15v figure 80 . input offset voltage vs. temperature ?50 ?100 ?150 ?200 ?250 ?40 125 input bias current (na) temperature (c) ?25 ?10 5 20 35 50 65 80 95 110 v sy = 15v v cm = 0v r l = i b + i b ? 08237-053 figure 81 . input bias current vs. temperature 1200 ?1200 ?15 ?10 ?5 5 10 15 input bias current (na) v cm (v) ?400 ?800 0 400 800 t a = +125c t a = ?40c v sy = 15v 0 t a = +25c t a = +85c 08237-054 figure 82 . input bias current vs. v cm for various temperatures 1000 10000 100 10 1 0.001 0.01 0.1 1 10 v do (mv) source current (ma) v sy = 15v t a = 25c (v+) ? v oh 08237-055 figure 83 . dropout voltage (v do ) vs. source current
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 25 of 35 1000 10000 100 10 1 0.001 0.01 0.1 1 10 v do (mv) sink current (ma) v sy = 15v t a = 25c v ol ? (v?) 08237-056 figure 84 . dropout voltage (v do ) vs. sink current 120 ?40 270 ?90 100 100m gain (db) phase (degrees) frequency (hz) ?45 0 45 90 135 180 225 ?20 20 0 40 60 80 100 1k 10k 100k 1m 10m v sy = 15v t a = 25c r l = 10k? 08237-057 figure 85 . open - loop gain and phase vs. frequency 60 ?20 10 100m gain (db) frequency (hz) ?10 0 10 20 30 40 50 100 1k 10k 100k 10m 1m v sy = 15v t a = 25c 08237-058 a v = +100 a v = +10 a v = +1 figure 86 . closed - loop gain vs. frequency 1000 100 10 1 0.1 0.01 10 100m z out (?) frequency (hz) 100 1k 10k 100k 10m 1m v sy = 15v t a = 25c a v = +100 a v = +1 a v = +10 08237-059 figure 87 . output impedance (z out ) vs. frequency 140 ?20 10 100m psrr (db) frequency (hz) 0 20 40 60 80 100 120 100 1k 10k 100k 10m 1m v sy = 15v t a = 25c psrr? psrr+ 08237-060 figure 88 . psrr vs. frequency 140 120 100 80 60 40 20 0 10 100m cmrr (db) frequency (hz) 100 1k 10k 100k 10m 1m v sy = 15v t a = 25c 08237-279 figure 89 . cmrr vs. frequency
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 26 of 35 15 10 ?15 ?10 ?5 0 5 0 4 8 12 36 28 32 24 20 16 voltage (v) time (s) v sy = 15v t a = 25c r l = 2k? c l = 100pf 08237-062 figure 90 . large signal transient response 80 60 40 20 0 ?80 ?60 ?40 ?20 0 2 1 4 3 7 8 9 6 5 10 voltage (mv) time (s) v sy = 15v t a = 25c r l = 2k? c l = 100pf 08237-063 figure 91 . small signal transient response 10 ?25 ?20 ?5 ?10 ?15 0 5 0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 ?2 0 2 4 8 6 18 16 12 10 14 voltage (v) voltage (v) time (s) v sy = 15v t a = 25c input output 08237-064 figure 92 . settling time 10 1 1 10 100 1k 10k 100k voltage noise density (nv/hz) frequency (hz) v sy = 15v t a = 25c 08237-065 4 figure 93 . voltage noise density vs. frequency 70 50 60 40 30 20 10 0 1 1000 100 10 overshoot (%) load capacitance (pf) v sy = 15v v in = 100mv p-p r l = 2k? t a = 25c os+ os? 08237-066 figure 94 . overshoot vs. load capacitance 0 2 4 6 8 10 60 ?60 voltage noise (nv) time (seconds) ?40 ?20 0 20 40 v sy = 15v t a = 25c 08237-067 figure 95 . voltage noise 0.1 hz to 10 hz
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 27 of 35 0 ?180 ?140 ?160 ?120 ?100 ?80 ?60 ?40 ?20 100 1k 10k 100k channel separation (db) frequency (hz) v sy = 15v t a = 25c v in = 10v p-p 08237-068 2k ? + 10v p-p ch a v cc v ee ? + 2k 10k 1k ch b, ch c, ch d v cc v ee figure 96 . channel separation vs. frequency 1 0.1 0.01 thd + n (%) 0.001 0.0001 0.001 0.01 amplitude (v rms ) 0.1 1 10 v sy = 15v r l = 10k v in at 1khz 08237-175 figure 97 . thd + n vs. amplitude 1 thd + n (%) 0.001 0.01 0.1 0.0001 0.01 0.1 frequenc y (khz) 1 10 100 v sy = 15v t a = 25c v in = 5v rms 500khz filter r l = 10k r l = 2k 08237-176 figure 98 . thd + n vs. frequency, 500 khz filter 0.1 0.01 0.001 0.00001 0.0001 10 100 1k 10k 100k thd + n (%) frequency (hz) 08237-289 v sy = 15v t a = 25c v in = 300mv rms 80khz filter r l = 2k r l = 10k 20 15 10 5 ?15 ?10 ?5 ?20 0 1000 voltage (v) time (s) 0 100 200 300 400 500 600 700 800 900 v sy = 15v t a = 25c output input 08237-071 figure 100 . no phase reversal ch2 5v ch1 100mv ch1 amp l 202mv m1s a ch1 ?84mv 1 2 t 10.2% 08237-178 v in v out v sy = 15v figure 101 . positive 50% overload recovery
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 28 of 35 ch2 5v ch1 100mv ch1 amp l 200mv m2 s a ch1 44mv 1 2 t 10.4% 08237-179 v in v out v sy = 15v figure 102 . negative 50% overload recovery 1000 0 0 36 i sy /amplifier (a) v sy (v) 100 200 300 400 500 600 700 800 900 4 8 12 16 20 24 28 32 t a = 25c r l = +125c +25c ?40c +85c 08237-072 figure 103 . supply current (i sy ) per amplifier vs. supply voltage (v sy ) for various temperatures ?50 ?25 0 25 50 75 100 125 150 cmrr (db) temper a ture (c) 0 20 60 40 80 100 120 140 v cm = 14v v cm = 1.5v v cm = 4v 08237-180 figure 104 . cmrr vs. temperature ?50 ?25 0 25 50 75 100 125 150 psrr (db) temper a ture (c) 50 60 80 70 90 100 120 150 140 130 1 10 v sy = 1.25v to 1.75v, v cm = 0v 08237-181 v sy = 2v to 18v, v cm = 0v figure 105 . psrr vs. temperature
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 29 of 35 applications informa tion functional descripti on the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 device s are precision single - supply, rail - to - rail operational amplifier s . intended for portable instrumentation, the a da4084 - 1 / ada4084 - 2 / ada4084 - 4 device s combin e the attributes of precision, wide bandwidth, and l ow noise , mak ing them an ideal choice in single - supply applications that require both ac and precision dc performance. other low supply voltage applications for which the ada4084 - 1 / ada4084 - 2 / a da4084 - 4 device s are well suited include active filters, audio microphone preamplifiers , power supply control, and telecommunications. to combine all of these attributes with rail - to - rail input/output operation, novel circuit design techniques are used. d2 d101 d100 d5 d4 d1 q1 q4 q3 q2 08237-073 r4 r1 r2 r3 figure 106 . equivalent input circuit for example, figure 106 illustrates a simplified equivalent circuit for the input stage of the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 . it comprises a p np differential pair, q1 and q2, and a n n pn differential pair, q3 and q4, operating concur - rently. diode d1 00 and diode d101 serve to clamp the applied differential input voltage to the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 , thereby protecting the input transistors against zener breakdown of the emitter - base junctions . in put stage voltage gains are kept low for input rail - to - rail operation. the two pairs of differential outpu t voltages are connected to the second stage of the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 , which is a modified compound folded cascade gain stage. it is also in the second gain stage that the two pairs of differential output voltages are combined into a single - ended output signal voltage used to drive the output stage. a key issue in the input stage is the behavior of the input bias currents over the input common - mode voltage range. input bias currents in the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 are the arithmetic sum of the base currents in q1 and q 4 and in q2 and q 3 . as a result, of this design approach, the input bias currents in the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 not only exhibit different amplitudes but they also exhibit different polarities. this effect is best illustrated by figure 19, figure 20, figure 50, figure 51, figure 81, and figure 82. it is , therefore , importan t that the effective source impedances that are connected to the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 inputs be balanced for optimum dc and ac performance. to achieve rail - to - rail output, the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 output stage design employs a unique topology for both sourcing and sinking current. this circuit topology is shown in figure 107 . the output stage is voltage driven from the second gain stage. the signal path through the output stage is inverting; that is, for positive input signals, q1 3 provides the base current drive to q 19 so that it conducts (sinks) current. for negative input signals, the signal path via q1 8 mirror q 2 4 provides the base current drive for q 23 to conduct (source) current. both transistors provide output current until they are forced into saturati on . q24 q21 d20 q13 q18 q19 q23 v ee v out v cc v bias mirror 08237-074 r5 r6 r7 c2 c1 figure 107 . equivalent output circuit thus, the saturation voltage of the output transistors sets the limit on the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 maximum output voltage swing. output short - circuit current limiting is determined by the maximum signal current into the base of q1 3 from the second gain stage. the output stage also exhibits voltage gain. this is accomplished by the use of com mon - emitter amplifiers, and, as a result, the voltage gain of the output stage (thus, the open - loop gain of the device) exhibits a dependence on the total load resistance at the output of the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 .
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 30 of 35 start -u p characteristics the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 are specified to operate from 3 v to 30 v (1.5 v to 15 v) under nomin al powe r supplies. during power - up as the supply voltage increases from 0 v to the nominal power supply voltage, the supply current (i sy ) increases as well , to the point at which it stabilizes and the amplifier is ready to operate. the stabilization varies with t emperature, as shown in figure 103 . for example , at ?40c , it requires a higher voltage and stabilizes at a lower supply current than at hot temperatures . at hot temperatures, it requires a lower voltage but stabilizes at a higher current. in all cases, the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 are specified to start up and operate at a m inimum of 3 v under all temperature conditions. input protection as with any semiconductor device, if conditions exist where the applied input voltages to the device exceed either supply voltage, the input overvoltage i - to - v characteristic of the device mu st be considered. when an overvoltage occurs, the amplifier may be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault current. the d1, d2, d4, and d5 diodes conduct when the input common - mode voltage exceeds eith er s upply pin by a diode drop. this diode drop voltage var ies with temperature and is in the range of 0.3 v to 0.8 v. as shown in the simplified equivalent input circuit of figure 106, the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 do not have any internal current limiting resistors; thus, fault currents can quickly rise to damaging levels. this input current is not inherently damaging to the device, provided that it is limited to 5 ma or less . if a fault condition cause s more than 5 ma to flow, add an external series resis tor at the expense of additional thermal noise. figure 108 shows a typical noninverting configuration for an overvoltage protected amplifier , where the series resistance ( r 1) is chosen , such that ( ) supply max in v v r1 ? = r1 r2 v in v out 1/2 ada4084-1/ ada4084-2/ ada4084-4 08237-075 figure 108 . resistance in series with the input limits overvoltage currents to safe values to protect the q1 / q2 and q3 / q4 pairs from large differential voltages that may result in zener breakdown of the emitter - base junction, d100 and d101 are connected between the two inputs. this precludes operation as a comparator. for a more complete description , see the mt - 035 tutorial , op amp inputs, outputs, single - supply, and rail - to - rail issues ; the mt - 083 tutorial , comparators ; the mt - 084 tutor ia l , using op amps a s comparators ; and the an - 849 application note , using op amps as comparators . output phase reversa l some operational amplifiers designed for single - supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common - mode range. typically, for single - supply bipolar op amps, the negative supply determines the l ower limit of their common - mode range. with these devices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excurs ions from exceeding the negative supply of the device (that is, gnd), preventi ng a condition that causes the output voltage to change p hase. jfet input amplifiers can also exhibit phase reversal , and, if so, a series input resistor is usually required to prevent it. the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 are free from reasonable input voltage range restrictions, provided that input voltages no greater than the supply voltages are applied (see figure 38, figure 69 , and figure 100). although device output does not change phase, large currents can flow through the input protection diodes. therefore, apply the technique recommended in the input protection section to those applications where the likelihood of input voltages exceed ing the supply voltages is high .
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 31 of 35 designing low noise circuits in singl e - supply applications in single - supply applications, devices like the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 extend the dynamic range of the application through the use of rail - to - rail op eration. referring to the op amp noise model circuit configuration illustrated in figure 109, t he expression for the total equivalent input noise vol tage o f an amplifier for a source resistance level, r s , is given by [ ] noa s noa nr nt e e e r i + + = (e nr ) 2 is the source resistance thermal noise voltage power (4 ktr) . k is the boltzmanns constant, 1.38 10 C 23 j/k. t is the ambient temperature in kelvin of the circuit, 273.15 + t a (c). ( i noa ) 2 is the op amp equivalent input noise current spectral power (1 hz bandwidth ). r s = 2 r, the effective, or equivalent, circuit source resistance. ( e noa ) 2 is the op amp equivalent input noise voltage spectral power (1 hz bandwidth). e nr e nr e noa i noa i noa r noiseless r noiseless 08237-076 ideal noiseless op amp r s = 2r figure 109 . op amp noise circuit model used to determine total circuit equivalent input noise voltage and noise figure as a design aid, figure 110 shows the equivalent thermal noise of the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 vs. the total source resi stance . note that for source resistance less than 1 k, the equivalent input noise voltage of the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 is dominant. 08237-077 total source resistance, r s ? 100 1 equivalent thermal noise (nv/ hz) 10 10k ada4084-1/ada4084-2/ada4084-4 total equivalent noise resistor thermal noise only 100 1k 100k frequency = 1khz t a = 25c figure 110 . equivalent thermal noise vs. total source resistance because c ircuit snr is the critical parameter in the final analysis, the noise behavior of a circuit is sometimes expressed in terms of its noise figure ( nf ) . the n oise fig ure is defined as the ratio of the signa l- to - nois e output of a circuit to its signal - to - noise input . noise figure is generally used for rf and microwave circuit analysis in a 50 ? system . this is not very useful for op amp circuits where the input and output impedances can vary greatly. for a more complete description of noise figure, see the mt - 052 tutorial , op amp noise figure: dont be misled . signal levels in the application invariably increase to maximize ci rcuit snr, which is not an option in low voltage, single - supply applications. t herefore, to achieve optimum circuit snr in single - supply applications, choose an operational amplifier with the lowest equivalent input noise voltage , along with source resistance levels that are consistent with maintaining low total circuit noise. comparator operation although op amps are quite different from comparators, occasionally an unused section of a dual or a quad op amp can be used as a comparator; however, this is not recommended for any rail - to - rail output op amps. for rail - to - rail output op amps, the output stage is generally a ratioed current mirror with bipolar or mosfet transistors. with the device operating open loop, the sec ond stage increases the current drive to the ratioed mirror to close the loop . however, the loop cannot close , which results in an increase in supply current. with the op amp configured as a comparator, the supply current can be significantly higher (see figure 111). configure a n unused section as a voltage followe r with the non inverting input connect ed to a voltage within the input voltage range. the ada4084 - 1 / ada4084 - 2 / ada4084 - 4 ha ve unique second stage and output stage design s that greatly reduce the excess supply current when the op amp is operating open loop . 800 0 0 36 supply current (a) v sy (v) 08237-078 100 200 300 400 500 600 700 4 8 12 16 20 24 28 32 t a = 25c r l ? comparator output low comparator output high buffer figure 111 . supply current vs. supply voltage (v sy )
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 32 of 35 outline dimensions c o n t r o l l i n g d i m e n s i o n s a r e i n m i l l i m e t e r s ; i n c h d i m e n s i o n s ( i n p a r e n t h e s e s ) a r e r o u n d e d - o f f m i l l i m e t e r e q u i v a l e n t s f o r r e f e r e n c e o n l y a n d a r e n o t a p p r o p r i a t e f o r u s e i n d e s i g n . c o m p l i a n t t o j e d e c s t a n d a r d s m s - 0 1 2 - a a 0 1 2 4 0 7 - a 0 . 2 5 ( 0 . 0 0 9 8 ) 0 . 1 7 ( 0 . 0 0 6 7 ) 1 . 2 7 ( 0 . 0 5 0 0 ) 0 . 4 0 ( 0 . 0 1 5 7 ) 0 . 5 0 ( 0 . 0 1 9 6 ) 0 . 2 5 ( 0 . 0 0 9 9 ) 4 5 8 0 1 . 7 5 ( 0 . 0 6 8 8 ) 1 . 3 5 ( 0 . 0 5 3 2 ) s e a t i n g p l a n e 0 . 2 5 ( 0 . 0 0 9 8 ) 0 . 1 0 ( 0 . 0 0 4 0 ) 4 1 8 5 5 . 0 0 ( 0 . 1 9 6 8 ) 4 . 8 0 ( 0 . 1 8 9 0 ) 4 . 0 0 ( 0 . 1 5 7 4 ) 3 . 8 0 ( 0 . 1 4 9 7 ) 1 . 2 7 ( 0 . 0 5 0 0 ) b s c 6 . 2 0 ( 0 . 2 4 4 1 ) 5 . 8 0 ( 0 . 2 2 8 4 ) 0 . 5 1 ( 0 . 0 2 0 1 ) 0 . 3 1 ( 0 . 0 1 2 2 ) c o p l a n a r i t y 0 . 1 0 figure 112 . 8 - lead standard small outline package [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-178-aa 10 5 0 s e a t i n g p l a n e 1 . 9 0 b s c 0 . 9 5 b s c 0 . 6 0 b s c 5 1 2 3 4 3 . 0 0 2 . 9 0 2 . 8 0 3 . 0 0 2 . 8 0 2 . 6 0 1 . 7 0 1 . 6 0 1 . 5 0 1 . 3 0 1 . 1 5 0 . 9 0 0 . 1 5 m a x 0 . 0 5 m i n 1 . 4 5 m a x 0 . 9 5 m i n 0 . 2 0 m a x 0 . 0 8 m i n 0 . 5 0 m a x 0 . 3 5 m i n 0 . 5 5 0 . 4 5 0 . 3 5 1 1-01-20 10-a figure 113 . 5 - lead small outline transistor package [sot - 23] (rj - 5) dimensions shown in millimeters
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 33 of 35 compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 114 . 8 - lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters t op view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a sea ting plane 0.80 0.75 0.70 1.70 1.60 sq 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed pin 1 indic a t or (r 0.15) 02-05-2013-b 0.20 min figure 115 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 12) dimensions shown in millimeters
ada4084 - 1/ada4084 - 2/ada4084 - 4 data sheet rev. h | page 34 of 35 compliant t o jedec standards mo-220-wggc. 042709 -a 1 0.65 bsc b o t t o m v i e w t o p v i e w 1 6 5 8 9 1 2 1 3 4 e x p o s e d p a d p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.50 0.40 0.30 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indica t or 0.35 0.30 0.25 2.60 2.50 sq 2.40 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 116 . 16 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 16 - 26) dimensions shown in millimeters compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 sea ting plane figure 117 . 14 - lead thin shrink small outline package [tssop] (ru - 14) dimensions shown in millimeters
data sheet ada4084 - 1/ada4084 - 2/ada4084 - 4 rev. h | page 35 of 35 ordering guide model 1 temperature range package description package option branding ada4084 - 1arz ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4084 - 1arz - r7 ?40c to +125c 8 - lead standard small outline package [soic_n] r - 8 ada4084 - 1arz - rl ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4084 - 1arjz -r2 ?40c to +125c 5- lead small outline transistor package [sot -23] rj -5 a38 ada4084 - 1arjz -r7 ?40c to +125c 5- lead small outline transistor package [sot -23] rj -5 a38 ada4084 - 1arjz -rl ?40c to +125c 5- lead small outline transistor package [sot -23] rj -5 a38 ada4084 - 2armz ?40c to +125c 8- lead mini small outline package [msop] rm -8 a2q ada4084 - 2armz -r7 ?40c to +125c 8- lead mini small outline package [msop] rm -8 a2q ada4084 - 2armz -rl ?40c to +125c 8- lead mini small outline package [msop] rm -8 a2q ada4084 - 2arz ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4084 - 2arz - r7 ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4084 - 2arz - rl ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4084 - 2acpz -r7 ?40c to +125c 8- lead lead frame chip scale package [lfcsp_wd] cp -8-12 a2q ada4084 - 2acpz -rl ?40c to +125c 8- lead lead frame chip scale package [lfcsp_wd] cp -8-12 a2q ada4084 - 4acpz -r7 ?40c to +125c 16- lead lead frame chip scale package [lfcsp_wq] cp -16-26 ada4084 - 4acpz -rl ?40c to +125c 16- lead lead frame chip scale package [lfcsp_wq] cp -16-26 ada4084 -4a ruz ?40c to +125c 14- lead thin shrink small outline package [tssop] ru -14 ada4084 -4a ruz -rl ?40c to +125c 14- lead thin shrink small outline package [tssop] ru -14 1 z = rohs compliant part. ? 2011 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08237 - 0 - 8/15(h)

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